Miniaturisation of technology is a continuing trend, especially in telecommunication systems. The ubiquitous analogue PLL is being replaced by All-digital PLLs (ADPLLs) and digital intensive PLLs where a degree of analogue circuitry remains. This is because these newer systems require a smaller area (PCB real-estate advantages), lower power consumption and increased scalability.
However, there remain problems to be solved before the analogue PLL can be entirely replaced, such as phase noise and spurious content as would be understood. At the current time, a traditional analogue PLL based on a charge pump (CP) and a loop filter (LPF) will still have better (less) phase noise and spurious content than its digital variant.
However, the CP requires lot of design effort since it usually dominates the in-band noise and may also contribute to spurious content. Additionally, the LPF is usually very large, and is often positioned outside the IC in question. There is a strong drive towards making the CP and LPF more digital intensive to reduce size, lower power consumption and improve noise response.
As shown in FIG. 1, a known integer-N ADPLL 10 (and also applying to a digital intensive PLL), comprises a phase frequency detector (PFD) 12 coupled to a a Time-To-Digital converter (TDC) 13 (which typically replaces the CP of a traditional analogue PLL). The TDC may comprise a Vernier topology comprising a plurality of steps (D-type latches) or any other suitable topology as would be understood. The TDC is coupled to a digital loop filter (LPF) 14 (which typically replaces the analogue LPF of a traditional analogue PLL), the LPF is coupled to a Digital Controlled Oscillator (DCO) 15 (which typically replaces the Voltage Controlled Oscillator (VCO) of a traditional analogue PLL). The PLL 10 also comprises a feedback loop 18 between the DCO 15 and the PFD 12 comprising a divider module 16 capable of dividing an input signal by an integer N. Operation of these components is known to the skilled person and so is not described herein.
As would be understood, in operation, PFD 12 is fed by a reference signal 11 having a frequency fR and a divided signal 17, the divided signal 17 being the result of the divider module 16 acting on DCO output 19. In operation, PLL 10 outputs DCO output 19 having frequency, fV=fR×N.
In an ADPLL 10, typically, the phase noise and spurious content are dominated by the TDC 13 performance due to its quantization nature. A better phase noise is achieved by a higher TDC resolution (as it is able to detect a smaller phase shift between its two inputs (11 and 17) from the PFD as would be understood).
The phase noise (PN) is calculated from:
                    PN        =                                                            (                                  2                  ⁢                  π                                )                            2                        12                    ⁢                                    f              V              2                                      f              R                                ⁢          Δ          ⁢                                          ⁢                      t            res            2                                              (        1        )            
Where fV is the DCO frequency (of DCO output 19), fR the reference frequency (of reference signal 11) and Δtres the TDC resolution. For example, to achieve a PN of −100 dBc with fV=3 GHz and fR=26 MHz, a TDC resolution of Δtres=9 ps is required, which means a TDC dynamic range of almost 40 steps (actually 37) to cover a full DCO period as would be understood.
FIG. 2 shows a fractional-N PLL 20. Features labelled with the same reference numerals as FIG. 1 are not described again. The divider module 166 can divide by a number of differing integer values (N+nk) and in effect, over a defined time period the divider module divides by an average value of (N+navg).
Notation N.n for divider 166 in the figures=N+n as would be understood where n=navg, the average value of nk.
The nk component of the integer values used may be provided by a sigma delta module (ΣΔ) 21. Module 21 that provides integer values nk may be any sequence generator where the average value of the sequence converges towards n which is a necessary condition for PLL locking at the desired frequency. The ΣΔ continuously changes the division factor of divider module 166 to provide the effective average value of n to generate a phase and frequency lock as would be understood. In operation, PLL 20 outputs DCO output 19 having frequency, fV=fR×N+n, where n is the average value of nk.
As is known, in order to obtain low fractional noise content, a higher-order ΣΔ is used to shift the noise outside of the bandwidth of the PLL in question (noise shaping). As the differing integer values used by the divider module 166 can place the divided signal 17 in different positions with respect to different periods of the DCO output 19, more than one DCO period needs to be covered by the TDC as would be understood. This results in a TDC with high dynamic range requirement when in a locked state resulting in high TDC current consumption, complexity and layout area, as the power and complexity scales at least linear with its dynamic range.
By way of example, the following table (table 1) shows both a low order ΣΔ input nk 22 (left hand side) and a high order input nk 22 (right hand side) to divider 166 in the fractional-N architecture of FIG. 2. In both cases the average value of n is 0.3 (as can be seen) and N of the divider module is initialised to 100. Over the 10 separate operations (at each clock cycle of reference signal 11) of the PLL, the output 24 from the TDC provides a digital signal proportional to the phase difference between reference signal 11 and divider signal 17 as detected by the PFD. As can be seen in this example, with a low order ΣΔ, TDC output 24 differs within two periods (−0.2 to 0.9) of DCO output 19. With a high order ΣΔ, TDC output 24 differs within (has a span of) eight periods (−2.2 to 3.7) of DCO output 19. Accordingly, with a high order ΣΔ (to reduce noise), the TDC requires a larger dynamic range to be able to cater for the full range of PFD outputs.
TABLE 1nkN_divTDC_OUTnkN_divTDC_OUT(22)(17)(24)(22)(17)(24)01000.301000.301000.6−3973.601000.911012.911010.231030.201000.5−1991.51101−0.24104−2.201000.1−3971.101000.411010.401000.7−3973.71101041040
There is therefore a need to reduce the requirements of the TDC (dynamic range) whilst maintaining PLL performance such as acceptable noise performance, low current consumption and acceptable resolution of the TDC.